Structure and method for single gate non-volatile memory device

ABSTRACT

The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a periphery region and a memory region; a field effect transistor disposed in the periphery region and having silicide features; and a single floating gate non-volatile memory device disposed in the memory region, free of silicide and having a first gate electrode and a second gate electrode laterally spaced from each other.

BACKGROUND

In deep sub-micron integrated circuit technology, non-volatile memorydevice has become a popular storage unit due to various advantages.Particularly, the data saved in the non-volatile memory device are notlost when the power is turned off. One particular example of thenon-volatile memory device includes a single floating gate to retain theelectrical charges associated with the saved data. When complementarymetal-oxide-semiconductor field effect transistor (CMOSFET) technologyis implemented, salicide is formed on various contact regions, such asgate, source and drain, to reduce the contact resistance. When theintegrated circuit including non-volatile memory device is scaled downthrough various technology nodes, the design of the memory device have aconsideration of the process integration, such as alignment margin andother factors, leading to large memory cell size and low packingdensity. Therefore, a structure of the single non-volatile memory deviceand a method making the same are needed to address the above issue.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isemphasized that, in accordance with the standard practice in theindustry, various features are not drawn to scale. In fact, thedimensions of the various features may be arbitrarily increased orreduced for clarity of discussion.

FIG. 1 is a flowchart of a method making a semiconductor device havingmetal gate stacks and polysilicon structures constructed according tovarious aspects of the present disclosure.

FIGS. 2-6 are sectional views of one embodiment of a semiconductorstructure having single floating gate non-volatile memory device atvarious fabrication stages constructed according to various aspects ofthe present disclosure.

FIGS. 7-10 are sectional views of a semiconductor structure havingsingle floating gate non-volatile memory device constructed according tovarious embodiments of the present disclosure.

FIGS. 11 and 12 are top views of a semiconductor structure having singlefloating gate non-volatile memory device constructed according to otherembodiments.

FIG. 13 is a top view of a semiconductor structure having singlefloating gate non-volatile memory device constructed according to otherembodiments.

FIG. 14 is a sectional view of the semiconductor structure of FIG. 13constructed according to other embodiments.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides manydifferent embodiments, or examples, for implementing different featuresof various embodiments. Specific examples of components and arrangementsare described below to simplify the present disclosure. These are, ofcourse, merely examples and are not intended to be limiting. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.Moreover, the formation of a first feature over or on a second featurein the description that follows may include embodiments in which thefirst and second features are formed in direct contact, and may alsoinclude embodiments in which additional features may be formedinterposing the first and second features, such that the first andsecond features may not be in direct contact.

FIG. 1 is a flowchart of an embodiment of a method 100 making asemiconductor device having a single floating gate non-volatile memorydevice constructed according to various aspects of the presentdisclosure. FIGS. 2 through 6 are sectional views of a semiconductorstructure 200 at various fabrication stages and constructed according toone or more embodiments. The semiconductor structure 200 and the method100 of making the same are collectively described with reference toFIGS. 1 through 6.

Referring to FIGS. 1 and 2, the method 100 begins at step 102 byproviding a semiconductor substrate 210. The semiconductor substrate 210includes silicon. Alternatively or additionally, the substrate includesgermanium, silicon germanium or other proper semiconductor materials.The semiconductor substrate 210 also includes various isolation featuressuch as shallow trench isolation (STI) formed in the substrate toseparate various devices. The semiconductor substrate also includesvarious doped regions such as n-well and p-wells. In one embodiment, thesemiconductor substrate 210 includes a periphery region 212 forperiphery devices and a memory region 214 for single floating gatenon-volatile memory devices. Various shallow trench isolation feature216 are formed in the semiconductor substrate 210 and are configured inthe periphery region 212 and the memory region 214 for proper electricalisolation. The formation of the STI may include etching a trench in asubstrate and filling the trench by insulator materials such as siliconoxide, silicon nitride, or silicon oxynitride. The filled trench mayhave a multi-layer structure such as a thermal oxide liner layer withsilicon nitride filling the trench. In one embodiment, the STI structuremay be created using a process sequence such as: growing a pad oxide,forming a low pressure chemical vapor deposition (LPCVD) nitride layer,patterning an STI opening using photoresist and masking, etching atrench in the substrate, optionally growing a thermal oxide trench linerto improve the trench interface, filling the trench with CVD oxide,using chemical mechanical planarization (CMP) to etch back, and usingnitride stripping to leave the STI structure. In another embodiment, thesemiconductor substrate 210 in the memory region 214 includes a dopedwell 218, such as an n-type doped well in one example.

The method 100 proceeds to step 104 by forming a first gate stack 220 inthe periphery region 212 and a second gate stack 222 and a third gatestack 224 in the memory region 214. In one embodiment, the first, secondand third gate stacks 220/222/224 are simultaneously formed in a sameprocessing procedure. The first gate stack 220 includes a first gatedielectric feature 226 a and a first gate electrode 228 a stacked on thefirst gate dielectric feature. Similarly, the second gate stack 222includes a second gate dielectric feature 226 b and a second gateelectrode 228 b stacked on the second gate dielectric feature, the thirdgate stack 224 includes a third gate dielectric feature 226 c and athird gate electrode 228 c stacked on the third gate dielectric feature.

In the present embodiment, various material layers, including a gatedielectric layer 226 and a gate electrode layer 228 are formed on thesubstrate 210 by various deposition technique. Then a lithographypatterning process is applied to the various material layers to patternthereof, forming the first, second and third gate stacks 220/222/224including respective gate dielectric features (226 a, 226 b and 226 c)and gate electrodes (228 a, 228 b and 228 c). In one example, the gatedielectric layer 226 includes silicon oxide and the gate electrode layer228 includes doped polysilicon. In another example, the gate dielectriclayer 226 of silicon oxide is formed by a thermal oxidation process andthe gate electrode layer 228 of polysilicon is formed by a chemicalvapor deposition (CVD) method. An exemplary lithography patterningprocess may include photoresist patterning, etching, and photoresiststripping. The photoresist patterning may further include processingsteps of photoresist coating, soft baking, mask aligning, exposingpattern, post-exposure baking, developing photoresist, and hard baking.Lithography patterning may also be implemented or replaced by otherproper methods such as maskless photolithography, electron-beam writing,ion-beam writing, and molecular imprint.

In one embodiment, various gate stacks may further include gate spacers(or sidewall spacers) 230 disposed on the sidewalls of the correspondinggate electrodes and are formed at a later step.

In an alternative embodiment, the first gate stack 220 can be formedseparately in a different procedure such that the first gate stack 220are configured differently from the second and third gate stacks222/224. For example, the first gate dielectric feature may have adifferent dielectric material and/or a different thickness from those ofthe second and third gate dielectric features.

In another alternative embodiment, the gate dielectric 226 may include ahigh-k dielectric layer. The high k dielectric layer includes adielectric material having the dielectric constant higher than that ofthermal silicon oxide, about 3.9. In one example, the high-k dielectriclayer includes hafnium oxide (HfO). In various examples, the high-kdielectric layer includes metal oxide, metal nitride, or combinationsthereof. In one embodiment, the gate electrode layer 228 includes metal,such as copper, aluminum or other suitable metal. In another embodiment,the gate stacks (e.g. 220, 222 and 224) may further include a conductivelayer interposed between the high-k dielectric layer and gate electrodelayer. In one example, the conductive layer includes titanium nitride(TiN).

In one embodiment, the gate stack 220 is configured for a firsttransistor 232, such as a field-effect transistor (FET). In one example,the first transistor 232 include a metal-oxide-semiconductor FET(MOSFET) such as n-type MOSFET or p-type MOSFET. The second gate stack222 is formed for a second transistor 234. In another embodiment, thethird gate stack 224 is formed for a capacitor 236. The secondtransistor 234 and the capacitor 236 are electrically coupled andconfigured to form a single floating gate non-volatile memory cell (ordevice). Particularly, the second gate electrode 228 b in the secondgate stack 222 is configured to be electrically floating. There is nocontrol gate directly stacked on the floating gate 228 b. The capacitor236 is coupled with the floating gate 228 b and further functions tocontrol various operations to the memory cell. As illustrated in FIG. 2,the second gate stack 222 and the third gate stack 224 are disposed atdifferent areas of the semiconductor substrate 210 and are laterallydistanced from each other. In this particular example, the second gatestack 222 and the third gate stack 224 are laterally separated by a STIfeature 216.

The method 100 proceeds to step 106 by forming various doped features inthe semiconductor substrate 210, including sources and drains in theperiphery region 212 and the memory region 214. The source and drain 238are formed for the first transistor 232 by a proper technique, such asone or more ion implantations. Similarly, source and drain 240 in thesecond transistor 234 are formed by a same process to form the sourceand drain 238 when both are same type (n-type or p-type) MOSFETs.Alternatively, the source and drain 240 in the second transistor 234 areseparately formed by similar technique when sources/drains 238 and 240are different type (one is n-type and another is p-type) MOSFETs. In oneembodiment, the source and drain features (238 and 240) further includelight doped source/drain (LDD) features substantially aligned with theassociated gate stack and heavily doped source/drain (S/D) featuressubstantially aligned with associated sidewall spacers 230. Infurtherance of the embodiment, taking the floating gate transistor 234as an example, the LDD features are formed first by ion implantationwith a light doping dose. Thereafter, the spacer 232 is formed bydielectric deposition and plasma etching. Then the heavily doped S/Dfeatures are formed by ion implantation with a heavy doping dose. Thevarious source and drain features of an nFET and a pFET can be formed ina similar procedure but with opposite doping type.

The doping type of the source/drain 138 is opposite from the doping typeof the semiconductor substrate 210 such that the first transistor 232 isproperly configured. As to the floating gate transistor 234, the dopingtype of the doped well 218 includes a first type of dopant and thesource/drain 240 includes a second type of dopant opposite from thefirst type of dopant. In the present embodiment, the doped well 218includes p-type dopant (p-well) and the source/drain 240 include n-typedopant, the corresponding floating gate transistor 234 is a n-typetransistor (nFET).

Particularly, doped region 241 is also formed in the capacitor 236. Inthe present embodiment, the doped region 241 is similar to thesource/drain 240 and includes the second type of dopant different fromthe first type of dopant in the doped well 218. The doped region 241 isdisposed at the edge of the gate stack 224 at one side. The doped region241 contacts the doped well 218 or disposed in the doped well 218.Alternatively, the doped region 241 is disposed on the both sides of thegate stack 224. In another alternative embodiment, the doped region 241includes the first type of dopant in the doped well. In yet anotherembodiment, the doped region 241 is simultaneously in the same ionimplantation procedure to form the source/drain 240. For example, thedoped region 241 may include a light doped feature and a heavily dopedfeature of the same type dopant, similar to the LDD and heavily dopedsource/drain 240. The doped well 218 serves as one capacitor electrodeand the third gate electrode 228 c is another capacitor electrode. Thegate dielectric feature 226 c is the capacitor dielectric sandwichedbetween the two capacitor electrodes.

Referring to FIG. 3, the method 100 proceeds to step 108 by forming hardmask layer 244 patterned to substantially cover the memory region 214while the periphery region 212 is exposed to subsequent silicideformation. Particularly, the source and drain 238 are exposed for thesilicide formation. Additionally, the first gate electrode 228 a may bealso exposed for silicide formation. The hard mask layer 244 includesvarious openings and is used for the subsequent silicide formation. Inone embodiment, the hard mask layer 244 includes openings, asillustrated in FIG. 3, to expose the gate stack 222 and the source/drain238 in the periphery region 212. The formation of the hard mask layer244 includes deposition and lithography patterning. The lithographypatterning includes forming a patterned photoresist layer on the hardmask layer and etching the hard mask layer through the openings of thepatterned photoresist layer. In one example, the hard mask layer 244includes silicon oxide formed by a CVD, such as plasma enhanced CVD(PECVD). In another embodiment, the etching process applied to the hardmask layer includes a hydrofluoric acid as the etchant to selectivelyremove the hard mask layer within the openings of the patternedphotoresist layer. The patterned photoresist layer may be removedthereafter by wet stripping or plasma ashing. The hard mask layer 244may include other suitable material such as silicon nitride according toanother embodiment. In one example, the silicon nitride hard mask layercan be formed by a suitable technique, such as PECVD. In one example,the thickness of the hard mask layer 244 ranges between about 200angstrom and about 1200 angstrom.

Still referring to FIG. 3, the method 100 proceeds to step 110 byforming various silicide features 246 in the periphery region 212 whilethe memory region 214 is protected by the hard mask from formingsilicide. The silicide features 246 are formed by a process known in theart such as self-aligned silicide (salicide) and therefore also referredto as salicide features 246. In one embodiment, the silicide features246 include nickel silicide. In an alternative embodiment, the silicidefeatures include 246 may include other suitable silicide, such as cobaltsilicide, tungsten silicide, tantalum silicide, titanium silicide,platinum silicide, erbium silicide, palladium silicide, or combinationsthereof. In one example, the silicide has a thickness ranging betweenabout 200 angstrom and about 800 angstrom.

The silicide features 246 are formed on the source/drain 238 and mayadditionally formed on the first gate electrode 228 a if the gate 228 aincludes polysilicon. In the present embodiment, the silicide features246 are selectively formed in the periphery region by utilizing the hardmask layer 244 patterned to cover the memory region 214. In one example,a metal layer is deposited on the hard mask layer 244 and on variouscontact regions (source/drain 238 and gate electrode 228 a) of thesemiconductor substrate 210 in the periphery region 212 aligned with theopenings of the hard mask layer 244. A high temperature annealing isapplied to the semiconductor substrate 210 and the metal layer such thatthe metal layer is reacted with silicon of the substrate 210 to formsilicide. The un-reacted metal layer is then removed by an etchingprocess, resulting the silicide features 246 as illustrated in FIG. 3.Another annealing process with a higher annealing temperature may befurther implemented to turn the silicide features 246 into a phase oflow resistivity. The hard mask layer 244 may stay after the formation ofthe silicide features 244.

The method 100 may proceed to step 112 by forming an etch stop layer(not shown on in FIG. 3) on the silicide features 246 and the hard masklayer 144. The etch stop layer includes a dielectric material chosen tohave etch selectivity for proper etch process at subsequent stages. Theetch stop layer may be conformal to the surface profile of thesemiconductor substrate 210 such that the etch stop layer substantiallycovers various features on the substrate.

Referring to FIG. 4, the method 100 proceeds to step 114 by forming aninter-level dielectric (ILD) layer 248 on the semiconductor substrate210 and the gate stacks 220/222/224. The ILD layer 248 is formed by asuitable technique, such as chemical vapor deposition (CVD). Forexample, a high density plasma CVD can be implemented to form the ILDlayer 248. The ILD layer 248 is formed on the substrate to a level abovethe top surface of the gate stacks 220/222/224 such that the gate stacks220/222/224 are embedded in. In various embodiments, the ILD layer 248includes silicon oxide, low-k dielectric material (dielectric materialwith dielectric constant less than about 3.9, the dielectric constant ofthe thermal silicon oxide). In various embodiments, the low-k materialincludes fluorinated silica glass (FSG), carbon doped silicon oxide,Black Diamond® (Applied Materials of Santa Clara, Calif.), Xerogel,Aerogel, amorphous fluorinated carbon, Parylene, BCB(bis-benzocyclobutenes), SiLK (Dow Chemical, Midland, Mich.), polyimide,and/or other suitable materials available or future developed.

In one embodiment, a chemical mechanical polishing (CMP) process isfurther applied to the ILD layer 248 to planarize the top surface of theILD layer 248. In another embodiment, the CMP process may further reducethe thickness of the ILD layer 248 such that the gate stacks 220/222/242are exposed from the top side. The processing conditions and parametersof the CMP process, including slurry chemical and polishing pressure,can be tuned to partially remove and planarize the ILD layer 248.

Referring to FIG. 5, the method 100 proceeds to step 116 by forming aplurality of contact holes 250 in the ILD layer 248 and aligned withvarious contact regions including the silicide features 246 in theperiphery region 212 and the source/drain 240 and the doped region 241in the memory region 214 such that those contact regions are exposed. Inanother example, a subset of the contact holes 250 may be formed andaligned with the gate stacks (e.g., 220, 222 and 224). The contact holes250 are formed by a lithography process and an etching process includingone or more etching steps. The etching process is applied to etch theILD layer 248 and the hard mask layer 244 to expose the contact regions.In one embodiment, the etching process includes an etch step using aplasma etch with a suitable etchant, such as fluorine-containingetchant, to selectively etch the ILD layer 248 and the hard mask layer244 without damaging to the silicide features in the periphery region212. In one example, the etch process uses plasma etch with as includingC5F8, CH2F2 and Ar. In furtherance of the example, the gas flows forC5F8, CH2F2 and Ar are tuned in ranges about 2 sccm˜30 sccm, 5 sccm˜40sccm, and 100 sccm˜600 sccm, respectively. In another embodiment, theetching process includes a first etch step (such as plasma etch) to etchthe ILD layer 248 and a second etch step using a wet etch with asuitable etchant, such as HF, to selectively remove the hard mask layer244 in the memory region 214 without damaging the silicide features 246in the periphery region 212.

Alternatively, if the etch stop layer is present, the second etch stepis tuned to selectively remove both the etch stop layer and the hardmask layer without damaging to the silicide features 246. In aparticular example, the second etch step is tuned such that etch ratesto the hard mask layer 244 and the etch stop layer are substantiallysame. In another embodiment, the etch stop layer is chosen to bedifferent from the ILD layer 248 and different from the hard mask layer244. For example, the ILD layer 248 includes silicon oxide or low-kdielectric material and the hard mask layer 244 includes silicon oxidewhile the etch stop layer includes silicon nitride or silicon carbide.

Referring to FIG. 6, the method 100 proceeds to step 118 by formingfilling the contact holes 250 with one or more metal, resulting contactfeatures or metal plugs. In one embodiment, tungsten is used to fill inthe contact holes to form tungsten plugs 252. Other metal, such ascopper or aluminum, can be used to form metal plugs 252. The metaldeposition can use physical vapor deposition (PVD), plating orcombination thereof. Another CMP process may be applied to removeexcessive metal layer formed on the ILD layer and to further planarizethe top surface of the semiconductor structure 200.

FIG. 7 illustrates a sectional view of the semiconductor structure 200having a floating gate non-volatile memory device constructed accordingto another embodiment. The floating gate non-volatile memory deviceincludes a floating gate transistor 234 and a capacitor 236 electricallycoupled together. The third gate electrode 228 c of the capacitor 236 iselectrically connected with the second gate electrode 228 b of thefloating gate transistor 234. Particularly, an interconnect structure256 is formed on the semiconductor substrate 210 on both the peripheryregion 212 and the memory region 214. The multilayer interconnectionincludes vertical interconnects, such as conventional vias or contacts,and horizontal interconnects, such as metal lines. The variousinterconnection features may implement various conductive materialsincluding copper, tungsten and silicide. In one example, a damasceneprocess is used to form copper related multilayer interconnectionstructure. In another embodiment, tungsten is used to form tungsten plugin the contact holes. Various contact holes are not shown in FIG. 7 forsimplicity. The interconnect structure 256 includes various features 258configured to electrically connect the gate electrodes 228 b and 228 cand further configured such that the gate electrodes 228 b and 228 c areelectrically floating (not operable and accessible to voltage bias).Alternatively, the silicide features 246 may not be present on the firstgate electrode 228 a in the periphery region 212.

Although the semiconductor structure 200 and the method 100 aredescribed, other alternatives and embodiments can be present withoutdeparture from the scope of the present disclosure. For example, thesingle floating gate non-volatile memory device in the memory region 214may have other suitable structures according to various otherembodiments and further provided below.

FIG. 8 illustrates another embodiment of a sectional view of asemiconductor structure 300 having a single floating gate non-volatilememory device 302. The semiconductor structure 300 is similar to thesemiconductor structure 200 as the single floating gate non-volatilememory device 302 in the memory region 214 is free of silicide. Thesilicide features 246 are formed on the first transistor 232 in theperiphery region 212 for enhanced device performance. However, thesemiconductor structure 300 includes a doped well 304 as one capacitorelectrode of the capacitor 236. The doped region 241 and the doped well304 include same type of dopants, such as both being n-type or bothbeing p-type. In the present embodiment, the semiconductor substrate 210is p-type doped. The doped well 304 is n-type doped. The source/drain240 and the doped region 241 are n-type doped. Particularly, the dopingconcentration of the doped region 241 is greater than that of the dopedwell 304 to reduce the voltage drop therebetween when a bias is appliedto the doped region 241.

FIG. 9 illustrates another embodiment of a sectional view of asemiconductor structure 310 having a single floating gate non-volatilememory device 312. The semiconductor structure 310 is similar to thesemiconductor structure 200 as the single floating gate non-volatilememory device 312 in the memory region 214 is free of silicide. Thesilicide features 246 are formed on the first transistor 232 in theperiphery region 212 for enhanced device performance. However, thesingle floating gate non-volatile memory device 312 includes a floatinggate transistor 234 and another transistor 314 integrated together. Thetransistor 314 includes a source 315 and a drain 316 disposed on theboth side of the gate stack 224. Particularly, the floating gatetransistor 234 and the transistor 314 are electrically coupled bysharing the common drain 316 interposed between the gate stacks 222 and224. The common drain 316 and the sources 240 and 315 can be formedsimultaneously in a same procedure. In the present embodiment, thesemiconductor substrate 210 includes a type of dopant opposite from thetype of dopant in the sources 240/315 and the common drain 316.Furthermore, the interconnect structure 256 includes various conductivefeatures 318 configured to couple the gate electrode 228 c of thetransistor 314 to an input for proper voltage bias. Comparably, the gateelectrode 228 b is configured to be electrically floating while the gateelectrode 228 c is configured to be electrically biased. In anotherexample, the single floating gate non-volatile memory device 312 may beformed in a doped well with a type dopant opposite from the sources (240and 315) and the common drain 316.

FIG. 10 illustrates another embodiment of a sectional view of asemiconductor structure 320 having a single floating gate non-volatilememory device 322. The semiconductor structure 320 is similar to thesemiconductor structure 310 as the single floating gate non-volatilememory device 322 in the memory region 214 is free of silicide. Thesilicide features 246 are formed on the first transistor 232 in theperiphery region 212 for enhanced device performance. However, thesingle floating gate non-volatile memory device 322 includes a floatinggate transistor 234 and another transistor 324 integrated together. Thetransistor 324 includes a source 315 and a drain 316 disposed on theboth side of the gate stack 224. Particularly, the floating gatetransistor 234 and the transistor 314 share the common drain 316interposed between the gate stacks 222 and 224. The common drain 316 andthe sources 240 and 315 can be formed simultaneously during a sameprocedure. In the present embodiment, the semiconductor substrate 210includes a type of dopant opposite from the type of dopant in thesources 240/315 and the common drain 316. Furthermore, the interconnectstructure 256 includes various conductive features 326 configured toconnect the gate electrode 228 c of the floating gate transistor 234 andthe gate electrode 228 c of the transistor 324. In one embodiment, thegate electrodes 228 b and 228 c are directly connected by another gateelectrode 228 d. The gate electrode 228 d is partially disposed on thecommon drain 316 and extended to the gate electrodes 228 b and 228 c,respectively, in a suitable configuration.

In one example illustrated in FIG. 11 as a top view of the singlefloating gate non-volatile memory device 322, the single floating gatenon-volatile memory device 322 includes source 240, source 315 and thecommon drain 316. The single floating gate non-volatile memory device322 further includes a gate electrode 228 (and gate dielectric 226 aswell, not shown) extended to the floating gate transistor 234 and thetransistor 324. The gate electrode 228 includes the first portion 228 bdisposed on the channel of the floating gate transistor 234, the secondportion 228 c disposed on the channel of the transistor 324 and thethird portion 228 d disposed on the common drain 316 configured in a waysuch that the gate electrodes 228 b and 228 c are connected. The singlefloating gate non-volatile memory device 322 further includes variouscontact 328 disposed and configured for various bias and electricalinput.

In another example, the single floating gate non-volatile memory device312 may be formed in a doped well with a type dopant opposite from thesources (240 and 315) and the common drain 316.

FIG. 12 illustrates a top view of the single floating gate non-volatilememory device 350 constructed according to another embodiment. Thesingle floating gate non-volatile memory device 350 is similar to thesingle floating gate non-volatile memory device 302 in FIG. 8. Thesingle floating gate non-volatile memory device 350 includes a floatingtransistor 234 and a capacitor 236 integrated together. In the presentembodiment, the single floating gate non-volatile memory device 350includes two floating gate non-volatile memory cells 352 and 354. Thefloating gate electrodes 228 are disposed on the channel of the floatinggate transistor 234 and extended to the capacitor 236, therefore, thegate stack on the channel of the transistor 234 are directly connectedwith the gate stack of the capacitor 236 since one floating gate 228extends over the both. The transistor 234 includes various source anddrain 240 and the capacitor 236 includes various doped regions 241.Furthermore, the doped well 304 is formed in the capacitor region andserves as one capacitor electrode. The doped regions 241 and the dopedwell 304 include a same type of dopant. In one example, the doped well304 is an n-type doped well (Nwell). The various contact regions in thesingle floating gate non-volatile memory device 350 are free ofsilicide.

The semiconductor structure having a single floating gate non-volatilememory device is illustrated in various embodiments, such as thesemiconductor structure 200 of FIG. 2. The semiconductor structure 200includes a periphery region and a memory region. The memory region issilicide free and includes one or more single floating gate non-volatilememory devices. The single floating gate non-volatile memory devices mayinclude a different structure, such as one illustrated in FIGS. 13 and14. FIG. 13 illustrates a top view of a single floating gatenon-volatile memory device 360 according to one or more embodiments.FIG. 14 illustrates a sectional view of the single floating gatenon-volatile memory device 360 along the line AA′ according to oneembodiment. The single floating gate non-volatile memory device 360 canbe incorporated in the semiconductor structure 200. The single floatinggate non-volatile memory device 360 is described with reference withFIGS. 2, 13 and 14.

The single floating gate non-volatile memory device 360 is alternativelyor additionally disposed in the memory region 214 that is free ofsilicide. The single floating gate non-volatile memory device 360includes a first cell 362 and a second cell 364 as an example. In thesingle floating gate non-volatile memory device 360, each cell (362 or364) includes an injection transistor (or first transistor) 234 and afloating gate transistor (or second transistor) 324 integrated together.Taking the second cell 364 as an example, the first transistor 234includes a source 240 and a drain 316 disposed on both sides of the gatestack 222. The second transistor 324 includes a source 315 and the drain316 disposed on both sides of the gate stack 224. Particularly, thefirst and second transistors 234/324 share the common drain 316interposed between the first gate stack 222 and the second gate stack224. The common drain 316 and the sources 240/315 can be formedsimultaneously during a same procedure. Each gate stack (222 or 224)includes a gate dielectric feature 226 on the substrate 210 and a gateelectrode 228 disposed on the corresponding gate dielectric feature 226.In the present embodiment, the gate stacks 222 and 224 in each cell forma continuous gate stack as illustrated in FIG. 13. Accordingly, the gateelectrode 228 b and 228 c are two portions of the continuous gateelectrode 228 and are electrically floating.

The single floating gate non-volatile memory device 360 further includesvarious contact features 328 embedded in the ILD layer 248. The contactfeatures 328 are configured to couple respective source and drain forvarious bias and electrical input. Each of the sources 240/315 anddrains 316 is coupled with one, two or more contact features 328. In oneexample, each common drain 316 is configured to couple with two contactfeatures 328. In the present embodiment, the source 240 is an injectionsource and the source 315 is a read source. In furtherance of thepresent embodiment, the contact feature 328 a is coupled to the readsource 315 and is further coupled to a read bit line; the contactfeature 328 b is coupled to the drain 316 and is further coupled to aword line; and the contact feature 328 c is coupled to the injectionsource 240 and is further coupled to an injection bit line.

In various embodiments of the semiconductor structure, the singlefloating gate non-volatile memory device in the memory region is free ofsilicide while the transistors (and other devices) in the peripheryregion include silicide features in various contact regions, such assource/drain and/or gate electrode. Various advantages may be present inone or more embodiments of the present disclosure. If non-silicidecontact feature is applied in the whole semiconductor structure, theperiphery circuits have degraded performance due to high contactresistance and high gate resisstance. If silicide features are formed onthe floating gate (no control gate overlying the floating gate in thesingle floating gate non-volatile memory device), it will degrade theintegrity of the floating gate data retention. When the silicidefeatures are formed on the source/drain regions of the single floatinggate non-volatile memory device, the design rules including the ruleconstraining the alignment margins between gate electrode and thesilicide feature and the rule constraining the alignment margins betweencontact plug and the silicide feature will lead to increased cell sizeand decreased packing density. The disclosed semiconductor structure invarious embodiments achieves the increased packing density withoutsacrifice of the periphery circuit performance and without degrading theintegrity of the floating gate data retention.

Other processing steps may be implemented before, during and/or afterthe formation of the semiconductor structure. For example, themultilayer interconnections are further formed after the step 118. Themultilayer interconnection includes vertical interconnects, such asconventional vias, and horizontal interconnects, such as metal lines.The various interconnection features may implement various conductivematerials including copper or aluminum. In one example, a damasceneprocess is used to form copper related multilayer interconnectionstructure.

The present disclosure is not limited to applications in which thesemiconductor structure includes a single floating gate non-volatilememory device in the memory region. Although embodiments of the presentdisclosure have been described in detail, those skilled in the artshould understand that they may make various changes, substitutions andalterations herein without departing from the spirit and scope of thepresent disclosure. For example, the semiconductor structures mayadditionally include other structure, such as a dynamic random accessmemory (DRAM) cell, a single electron transistor (SET), fieldprogrammable gate-array (FPGA) and/or other microelectronic devices(collectively referred to herein as microelectronic devices). In anotherembodiment, the semiconductor structure includes FinFET transistors. Ofcourse, aspects of the present disclosure are also applicable and/orreadily adaptable to other type of transistor, including single-gatetransistors, double-gate transistors and other multiple-gatetransistors, and may be employed in many different applications,including sensor cells, logic cells, and others.

Thus, the present disclosure provides an integrated circuit. Theintegrated circuit includes a semiconductor substrate having a peripheryregion and a memory region; a field effect transistor disposed in theperiphery region and having silicide features; and a single floatinggate non-volatile memory device disposed in the memory region, free ofsilicide and having a first gate electrode and a second gate electrodelaterally spaced from each other.

In one embodiment, the single floating gate non-volatile memory devicein the memory region includes a first region and a second regionapproximate the first region, wherein the first region includes a firststructure and the second region includes a second structure. The firststructure is designed operable to store charges and includes a firstgate dielectric feature over the semiconductor substrate; the first gateelectrode disposed on the first gate dielectric feature and configuredto be floating; and source and drain formed in the semiconductorsubstrate, disposed on both sides of the first gate electrode. Thesecond structure is coupled with the first structure for dataoperations, and includes a second gate dielectric feature over thesemiconductor substrate; and the second gate electrode disposed on thesecond gate dielectric feature.

In another embodiment, the first structure is configured as a transistorwith a floating gate coupled with the second gate electrode and thesecond structure is configured as a capacitor. In yet anotherembodiment, the second structure further includes a doped well of afirst type dopant formed in the semiconductor substrate and underlyingthe second gate electrode; and a doped contact of the first type dopantformed in the semiconductor substrate and contacting the doped well,wherein the capacitor includes the doped well as a first capacitorelectrode, the second gate electrode as a second capacitor electrode,and the second gate dielectric feature as a capacitor dielectricsandwiched between the first and second capacitor electrodes. In yetanother embodiment, the second structure further includes a doped wellof a first type dopant formed in the semiconductor substrate andunderlying the second gate electrode; and a doped contact of a secondtype dopant formed in the semiconductor substrate and contacting thedoped well, the second type dopant being opposite to the first typedopant, wherein the capacitor includes the doped well as a firstcapacitor electrode, the second gate electrode as a second capacitorelectrode, and the second gate dielectric feature as a capacitordielectric sandwiched between the first and second capacitor electrodes.

In another embodiment, the first structure is configured as a floatinggate transistor and the second structure is configured as a selecttransistor serially connected with the floating gate transistor; theselect transistor and the floating gate transistor share the drain. Inyet another embodiment, the first structure is configured as a floatinggate transistor and the second structure is configured as an injectiontransistor; the injection transistor and the floating gate transistorshare the drain; and the second gate electrode is electrically connectedwith the first gate electrode. The field effect transistor in theperiphery region may include a third gate disposed on a third gatedielectric feature; a source and a drain formed in the semiconductorsubstrate and interposed by the third gate; and the silicide featuresformed on the source, drain and the third gate of the field effecttransistor in the periphery region, and being further coupled to aninterconnect structure for respective electrical bias. The second gatemay be electrically connected to the first gate and is electricallyfloating.

The present disclosure also provides another embodiment of an integratedcircuit. The integrated circuit includes a semiconductor substratehaving a periphery region and a memory region, wherein the peripheryregion includes silicide features disposed on various contact areas andthe memory region is free of silicide; and a plurality of singlefloating gate non-volatile memory cells disposed in the memory region.Each of the single floating gate non-volatile memory cells includes afirst gate electrode disposed on the semiconductor substrate, separatedby a first gate dielectric feature from the semiconductor substrate andconfigured to be floating for storing charges; a source and a drainformed in the semiconductor substrate, respectively disposed on bothsides of the first gate; and a second gate electrode disposed on thesemiconductor substrate, separated by a second gate dielectric featurefrom the semiconductor substrate and laterally distanced from the firstgate electrode.

In one embodiment, the second gate electrode is electrically connectedwith an interconnect structure for electrical bias. The integratedcircuit may further include a source in the semiconductor substrate anddisposed at an edge of the second gate electrode, wherein the secondgate electrode is electrically connected with the first gate electrodeand the source at the edge of the second gate electrode is configuredoperable to charge the first gate electrode. The integrated circuit mayfurther include a first doped region of a first type dopant in thesemiconductor substrate and directly underlying the second gateelectrode; and a second doped region of the first type dopant in thesemiconductor substrate and contacting the first doped region, whereinthe second gate electrode is electrically connected with the first gateelectrode, and the second doped region is configured operable to chargethe first gate electrode. In another embodiment, the single floatinggate memory device in the memory region includes a first region and asecond region approximate the first region; the first region includesthe first gate dielectric feature, the first gate electrode, the sourceand the drain configured as a transistor; the second region includes adoped well in the semiconductor substrate and directly underlying thesecond gate dielectric feature, the second gate dielectric feature, andthe second gate electrode configured as a capacitor; and the second gateelectrode is electrically connected with the first gate electrode. Inyet another embodiment, the integrated circuit further include a shallowtrench isolation (STI) in the semiconductor substrate and disposedbetween the drain of the transistor and the doped well.

In yet another embodiment, the integrated circuit further includes ahard mask layer of a first dielectric material on the semiconductorsubstrate within the memory region; an etch stop layer of a seconddielectric material on the semiconductor substrate and partially on thehard mask layer; an inter-level dielectric (ILD) layer of a thirddielectric material on the etch stop layer; a first plurality of contactfeatures in the memory region and embedded in the hard mask layer, theetch stop layer and the ILD layer; and a second plurality of contactfeatures in the periphery region, embedded in the hard mask layer, theetch stop layer and the ILD layer and contacting the silicide features.The second dielectric material is different from the first dielectricmaterial and the third dielectric material.

The present disclosure also provides an embodiment of a method of makingan integrated circuit. The method includes providing a silicon substratehaving a memory region and a periphery region; forming a gate dielectriclayer on the silicon substrate and a gate electrode layer on the gatedielectric layer; patterning the gate electrode layer and the gatedielectric layer, resulting in a first gate stack and a second gatestack in the memory region and a third gate stack in the peripheryregion, the second gate stack being laterally distanced from the firstgate stack; performing various implantations to the silicon substrate,forming a first source and a first drain on both sides of the first gatestack and a second source and a second drain on both sides of the thirdgate stack; and forming a hard mask layer on the silicon substrate,wherein the hard mask layer covers the memory region and exposes thethird gate stack, the second source and the second drain in theperiphery region; and forming silicide on the third gate stack, thesecond source and the second drain in the periphery region while thememory region is protected from forming silicide by the hard mask layer.

In one embodiment, forming silicide includes depositing a metal layer onthe silicon substrate through the hard mask layer; performing anannealing process to the silicon substrate to react the metal layer withthe silicon substrate; and etching to remove un-reacted portion of themetal layer. In another embodiment, after forming silicide, the methodfurther includes forming an inter-level dielectric (ILD) layer on thesilicon substrate; etching the ILD layer to form contact holes,respectively aligned with the first source and first drain in the memoryregion and the second source and the second drain in the peripheryregion; etching the hard mask layer within the contact holes of thememory region; and forming conductive plugs in the contact holes. Inanother embodiment, etching the hard mask layer includes implementing anetching process tuned to selectively etch the hard mask layer withoutsignificant damage to the silicide within the contact holes of theperiphery region. In yet another embodiment, before forming conductiveplugs, the method further includes forming an etch stop layer on thesilicon substrate before forming an ILD layer such that the etch stoplayer is overlying the hard mask layer and the silicide and isunderlying the ILD layer; etching the etch stop layer after etching theILD layer; and thereafter etching the hard mask layer.

In yet another embodiment, the method, before forming conductive plugs,further includes forming an etch stop layer on the silicon substratebefore forming an ILD layer such that the etch stop layer is overlyingthe hard mask layer and the silicide and is underlying the ILD layer;and performing an etching process to the etch stop layer and the hardmask layer after etching the ILD layer, wherein the etching process istuned to substantially remove the etch stop layer and the hard masklayer without damage to the silicide features.

The foregoing has outlined features of several embodiments. Thoseskilled in the art should appreciate that they may readily use thepresent disclosure as a basis for designing or modifying other processesand structures for carrying out the same purposes and/or achieving thesame advantages of the embodiments introduced herein. Those skilled inthe art should also realize that such equivalent constructions do notdepart from the spirit and scope of the present disclosure, and thatthey may make various changes, substitutions and alterations hereinwithout departing from the spirit and scope of the present disclosure.

1. An integrated circuit, comprising: a semiconductor substrate having aperiphery region and a memory region; a field effect transistor disposedin the periphery region and having silicide features; and a singlefloating gate non-volatile memory device disposed in the memory region,free of silicide and having a first gate electrode and a second gateelectrode laterally spaced from each other.
 2. The integrated circuit ofclaim 1, wherein the single floating gate non-volatile memory device inthe memory region includes a first region and a second regionapproximate the first region, wherein the first region includes a firststructure and the second region includes a second structure; the firststructure is designed operable to store charges and includes: a firstgate dielectric feature over the semiconductor substrate; the first gateelectrode disposed on the first gate dielectric feature and configuredto be floating; and source and drain formed in the semiconductorsubstrate, disposed on both sides of the first gate electrode; and thesecond structure is coupled with the first structure for dataoperations, and includes: a second gate dielectric feature over thesemiconductor substrate; and the second gate electrode disposed on thesecond gate dielectric feature.
 3. The integrated circuit of claim 2,wherein the first structure is configured as a transistor with afloating gate coupled with the second gate electrode and the secondstructure is configured as a capacitor.
 4. The integrated circuit ofclaim 3, wherein the second structure further includes: a doped well ofa first type dopant formed in the semiconductor substrate and underlyingthe second gate electrode; and a doped contact of the first type dopantformed in the semiconductor substrate and contacting the doped well,wherein the capacitor includes the doped well as a first capacitorelectrode, the second gate electrode as a second capacitor electrode,and the second gate dielectric feature as a capacitor dielectricsandwiched between the first and second capacitor electrodes.
 5. Theintegrated circuit of claim 3, wherein the second structure furtherincludes: a doped well of a first type dopant formed in thesemiconductor substrate and underlying the second gate electrode; and adoped contact of a second type dopant formed in the semiconductorsubstrate and contacting the doped well, the second type dopant beingopposite to the first type dopant, wherein the capacitor includes thedoped well as a first capacitor electrode, the second gate electrode asa second capacitor electrode, and the second gate dielectric feature asa capacitor dielectric sandwiched between the first and second capacitorelectrodes.
 6. The integrated circuit of claim 2, wherein the firststructure is configured as a floating gate transistor and the secondstructure is configured as a select transistor serially connected withthe floating gate transistor; and the select transistor and the floatinggate transistor share the drain.
 7. The integrated circuit of claim 2,wherein the first structure is configured as a floating gate transistorand the second structure is configured as an injection transistor; theinjection transistor and the floating gate transistor share the drain;and the second gate electrode is electrically connected with the firstgate electrode.
 8. The integrated circuit of claim 7, wherein the sourceof the floating gate transistor is coupled to a read bit line; the drainis coupled to a word line; and a source of the injection transistor iscoupled to an injection bit line.
 9. The integrated circuit of claim 2,wherein the field effect transistor in the periphery region includes: athird gate disposed on a third gate dielectric feature; a source and adrain formed in the semiconductor substrate and interposed by the thirdgate; and the silicide features formed on the source, drain, and thethird gate of the field effect transistor in the periphery region, andbeing further coupled to an interconnect structure for respectiveelectrical bias.
 10. The integrated circuit of claim 2, wherein thesecond gate is electrically connected to the first gate and iselectrically floating.
 11. An integrated circuit, comprising: asemiconductor substrate having a periphery region and a memory region,wherein the periphery region includes silicide features disposed onvarious contact areas and the memory region is free of silicide; and aplurality of single floating gate non-volatile memory cells disposed inthe memory region, wherein each of the single floating gate non-volatilememory cells includes: a first gate electrode disposed on thesemiconductor substrate, separated by a first gate dielectric featurefrom the semiconductor substrate and configured to be floating forstoring charges; a source and a drain formed in the semiconductorsubstrate, respectively disposed on both sides of the first gate; and asecond gate electrode disposed on the semiconductor substrate, separatedby a second gate dielectric feature from the semiconductor substrate andlaterally distanced from the first gate electrode.
 12. The integratedcircuit of claim 11, wherein the second gate electrode is electricallyconnected with an interconnect structure for electrical bias.
 13. Theintegrated circuit of claim 11, further comprising a source in thesemiconductor substrate and disposed at an edge of the second gateelectrode, wherein the second gate electrode is electrically connectedwith the first gate electrode and the source at the edge of the secondgate electrode is configured operable to charge the first gateelectrode.
 14. The integrated circuit of claim 11, further comprising afirst doped region of a first type dopant in the semiconductor substrateand directly underlying the second gate electrode; and a second dopedregion of the first type dopant in the semiconductor substrate andcontacting the first doped region, wherein the second gate electrode iselectrically connected with the first gate electrode, and the seconddoped region is configured operable to charge the first gate electrode.15. The integrated circuit of claim 11, wherein the single floating gatememory device in the memory region includes a first region and a secondregion approximate the first region; the first region includes the firstgate dielectric feature, the first gate electrode, the source and thedrain configured as a transistor; the second region includes a dopedwell in the semiconductor substrate and directly underlying the secondgate dielectric feature, the second gate dielectric feature, and thesecond gate electrode configured as a capacitor; and the second gateelectrode is electrically connected with the first gate electrode. 16.The integrated circuit of claim 15, further comprising a shallow trenchisolation (STI) in the semiconductor substrate and disposed between thedrain of the transistor and the doped well.
 17. The integrated circuitof claim 11, further comprising a hard mask layer of a first dielectricmaterial on the semiconductor substrate within the memory region; anetch stop layer of a second dielectric material on the semiconductorsubstrate and partially on the hard mask layer; an inter-leveldielectric (ILD) layer of a third dielectric material on the etch stoplayer; a first plurality of contact features in the memory region andembedded in the hard mask layer, the etch stop layer, and the ILD layer;and a second plurality of contact features in the periphery region,embedded in the hard mask layer, the etch stop layer and the ILD layerand contacting the silicide features, wherein the second dielectricmaterial is different from the first dielectric material and the thirddielectric material.
 18. A method of making an integrated circuit, themethod comprising: providing a silicon substrate having a memory regionand a periphery region; forming a gate dielectric layer on the siliconsubstrate and a gate electrode layer on the gate dielectric layer;patterning the gate electrode layer and the gate dielectric layer,resulting in a first gate stack and a second gate stack in the memoryregion and a third gate stack in the periphery region, the second gatestack being laterally distanced from the first gate stack; performingvarious implantations to the silicon substrate, forming a first sourceand a first drain on both sides of the first gate stack and a secondsource and a second drain on both sides of the third gate stack; forminga hard mask layer on the silicon substrate, wherein the hard mask layercovers the memory region and exposes the third gate stack, the secondsource and the second drain in the periphery region; and formingsilicide on the third gate stack, the second source and the second drainin the periphery region while the memory region is protected fromforming silicide by the hard mask layer.
 19. The method of claim 18,wherein forming silicide includes: depositing a metal layer on thesilicon substrate through the hard mask layer; performing an annealingprocess to the silicon substrate to react the metal layer with thesilicon substrate; and etching to remove un-reacted portion of the metallayer.
 20. The method of claim 18, after forming silicide, furthercomprising: forming an inter-level dielectric (ILD) layer on the siliconsubstrate; etching the ILD layer to form contact holes, respectivelyaligned with the first source and first drain in the memory region andthe second source and the second drain in the periphery region; etchingthe hard mask layer within the contact holes of the memory region; andforming conductive plugs in the contact holes.
 21. The method of claim20, wherein etching the hard mask layer includes implementing an etchingprocess tuned to selectively etch the hard mask layer withoutsignificant damage to the silicide within the contact holes of theperiphery region.
 22. The method of claim 20, before forming conductiveplugs, further comprising forming an etch stop layer on the siliconsubstrate before forming an ILD layer such that the etch stop layer isoverlying the hard mask layer and the silicide and is underlying the ILDlayer; etching the etch stop layer after etching the ILD layer; andthereafter etching the hard mask layer.
 23. The method of claim 20,before forming conductive plugs, further comprising forming an etch stoplayer on the silicon substrate before forming an ILD layer such that theetch stop layer is overlying the hard mask layer and the silicide and isunderlying the ILD layer; and performing an etching process to the etchstop layer and the hard mask layer after etching the ILD layer, whereinthe etching process is tuned to substantially remove the etch stop layerand the hard mask layer without damage to the silicide features.